Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering SCHIE is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AISiE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Principal Physical Design Engineer to join the team.
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Responsibilities
We are looking to expand our Physical Design Engineer team in US with immediate hiring of a few senior and principal level Physical Design engineers to work on Microsoft Next-Gen AI SOC chip. If hired, you will be responsible for delivering TFM tool, flow and methodology of Physical Design tasks at block, sub-chip, and/or full-chip level. The roles include one or more of the following tasks - Place and Route PnR, Static Timing Analysis STA and timing ECOs, Physical Verification PV, Formal Equivalency Verification FEV, Functional ECO, Global Clocking Construction, IR-Drop/EM EMIR and PD Infrastructure and IPs collaterals handling with details below:
· Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level
· Develop and implement methodologies and strategies to improve physical design efficiency and performance
· Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing analysis, physical verification, functional logics equivalence, low power verification and electromigration and IR drop
· Implementation of functional and timing ECO with least physical design impact
· Design and implement the global clocking scheme at SOC and sub chip levels
· Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies
· Installation and quality check of int
