Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering SCHIE is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering CSME organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Fabric IP Design team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Fabric IP Designer to join the team to support our mission.
#SCHIE #CSME
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
Be part of a design team developing advanced components of the memory sub-system
Develop automation and AI based solutions to improve organizational efficiency
Own design blocks within complex, coherent fabrics, and bridge IPs
Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc
Collaborate with team members to define interfaces and make optimal design choices
Work with verification teams to develop test plans and ensure functional correctness
Interface with performance modeling, physical design, design for test, and other teams to optimize tradeoffs
Qualifications
Required Qualifications:
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
